module sdc_av_wrap (
           clk,
           reset_n,
           // av_slave
           as_address,
           as_chipselect,
           as_write,
           as_read,
           as_writedata,
           as_readdata,
           as_byteenable,
           as_waitrequest_n,

           // av_master
           am_address,
           am_read,
           am_write,
           am_byteenable,
           am_readdata,
           am_readdatavaild,
           am_writedata,
           am_waitrequest_n,

           // interrupt
           irq_cmd,
           irq_data,

           // sdio
           sd_clk,
           sd_cmd,
           sd_dat
       );

input                   clk;
input                   reset_n;
//avalon slave port
input  [7:0]            as_address;
input                   as_chipselect;
input                   as_write;
input                   as_read;
input  [31:0]           as_writedata;
input  [3:0]            as_byteenable;
output [31:0]           as_readdata;
output                  as_waitrequest_n;
//avalon master port
output [31:0]               am_address;
output                      am_read;
output                      am_write;
output [3:0]                am_byteenable;
input  [31:0]               am_readdata;
input                       am_readdatavaild;
output [31:0]               am_writedata;
input                       am_waitrequest_n;
//sdio port
output      sd_clk;
inout       sd_cmd;
inout[3:0]  sd_dat;

output irq_cmd;
output irq_data;

wire m_wb_we_o;
wire m_wb_cyc_o;
wire m_wb_stb_o;

assign am_read = m_wb_stb_o & (~m_wb_we_o);
assign am_write = m_wb_stb_o & m_wb_we_o;

wire sd_cmd_dat_i;
wire sd_cmd_out_o;
wire sd_cmd_oe_o;

assign sd_cmd = sd_cmd_oe_o ? sd_cmd_out_o : 1'bz;
assign sd_cmd_dat_i = sd_cmd;

wire[3:0]   sd_dat_dat_i;
wire[3:0]   sd_dat_out_o;
wire        sd_dat_oe_o;

assign sd_dat = sd_dat_oe_o ? sd_dat_out_o : 4'hz;
assign sd_dat_dat_i = sd_dat;

wire sd_clk_o_pad;

sdc_controller sdc(
                   .wb_clk_i(clk),
                   .wb_rst_i(~reset_n),

                   // Slave
                   .wb_dat_i(as_writedata),
                   .wb_dat_o(as_readdata),
                   .wb_adr_i(as_address),
                   .wb_sel_i(as_byteenable),
                   .wb_we_i(as_write & ~as_read),
                   .wb_stb_i(as_chipselect & (as_write | as_read)),
                   .wb_cyc_i(as_write | as_read),
                   .wb_ack_o(as_waitrequest_n),

                   // Master
                   .m_wb_adr_o(am_address),
                   .m_wb_dat_o({am_writedata[7:0], am_writedata[15:8], am_writedata[23:16], am_writedata[31:24]}), // BE to LE
                   .m_wb_dat_i({am_readdata[7:0], am_readdata[15:8], am_readdata[23:16], am_readdata[31:24]}), // BE to LE
                   .m_wb_sel_o(am_byteenable),
                   .m_wb_we_o(m_wb_we_o),
                   .m_wb_ack_i(am_waitrequest_n),
                   .m_wb_cyc_o(m_wb_cyc_o),
                   .m_wb_stb_o(m_wb_stb_o),

                   // SDIO
                   .sd_cmd_dat_i(sd_cmd_dat_i),
                   .sd_cmd_out_o(sd_cmd_out_o),
                   .sd_cmd_oe_o(sd_cmd_oe_o),
                   .sd_dat_dat_i(sd_dat_dat_i),
                   .sd_dat_out_o(sd_dat_out_o),
                   .sd_dat_oe_o(sd_dat_oe_o),
                   .sd_clk_o_pad(sd_clk),
                   .sd_clk_i_pad(clk),

                   .int_cmd(irq_cmd),
                   .int_data(irq_data)
               );

endmodule
